This invention relates to angled ion implants. More particularly, it relates to a method of producing a symmetrical and an asymmetrical semiconductor device using angled ion implantation.
Semiconductor devices, such as metal oxide semiconductor field effect transistors (MOSFETs), produced with angled ion implantation techniques are often constructed symmetrically. This allows great flexibility in the layout of multiple devices as the source and drain are interchangeable (and both sides of the gate are consequently referred to simply as the xe2x80x9csource/drainxe2x80x9d).
For some applications, this type of device symmetry is highly desirable or essential. Devices produced by angled ion implantation are generally made symmetric by rotating the semiconductor device to allow the angled implant beam to implant from all sides of the gate. This results in a series of symmetrical implants and a symmetrical device.
High voltage devices have required a graded lightly doped drain (LDD) implant while low voltage devices favor an abrupt implant, such as an extension type implant, as is well known in the art. Low voltage devices also often have a halo or a more heavily doped halo than high voltage devices. Such high and low voltage devices are frequently fabricated on the same chip. They generally have different gate dielectric thicknesses, channel lengths, and use separate masking steps and implants for the source/drain design.
For other applications, performance can be improved if the semiconductor device is constructed asymmetrically. For example, for MOSFETs having an LDD region and a halo region, the LDD is desirable exclusively on the drain side and the halo is desirable exclusively on the source side of the gate.
The addition of an LDD region degrades device performance because it increases series resistance and overlap capacitance. Since the lightly doped LDD region is strictly required only on the drain side of the device to mitigate hot carrier degradation, the LDD on the source side of a symmetrical device adds series resistance and capacitance with no additional benefit. Device performance can be improved if the LDD implant could be blocked from the source side thereby making an asymmetrical device. Furthermore, where a particular device is never subjected to high voltages, blocking the LDD implant from both sides may also be advantageous.
However, a very accurately-aligned critical mask capable of blocking the implant beam from the source side, but not blocking it from the drain side, has been needed to provide the desired asymmetrical device. To block the implant on one side, but not on the other side of the gate requires aligning the critical mask to within the width of the gate. This has required alignment tolerance within one half the width of the gate. Obtaining such critical alignment is an expensive and error-prone procedure.
Alternatively, the LDD implant may be produced through a single ion implant beam which places the implant under one side of the gate. Thus, the desired LDD is formed when the appropriate ion implant beam is directed at an angle towards the drain side of the gate. To produce many asymmetrical devices on the same semiconductor substrate requires that all of the devices be oriented in the same direction so that a single ion implant step can produce all of the LDD regions desired on the same side of the gate while avoiding implant on the opposite side.
It can be seen that controlled device asymmetry is possible if all the devices are oriented in the same direction and the opposite direction rotation is omitted. However, orienting all of the devices in the same direction significantly limits layout flexibility.
The same problem is encountered when constructing a halo implant only on the source side of the device. If the halo implant is placed on the drain side, it increases junction capacitance and peak electric field. Achieving halo implants only on the source side has heretofore required the same choice between an expensive critical mask with alignment comparable to half the gate width or an angle implant with uniform device orientation such that all of the devices have the source on the same side.
Therefore, an improved process to provide implants is needed and this solution is provided by the following invention.
It is therefore an object of the present invention to selectively provide different implants on different devices or on different sides of the same device on a semiconductor wafer.
It is a further object of the present invention to form both symmetrical and asymmetrical semiconductor devices on a semiconductor wafer.
It is a feature of the present invention to use a single non-critical mask to selectively form barriers adjacent semiconductor devices or adjacent one side of certain devices to shadow ion implant beams.
It is an advantage of the present invention that the location of ion implant can be controlled without adding critical masks or reducing layout flexibility.
It is an advantage of the present invention to provide asymmetrical devices without added critical masks or reducing layout flexibility.
These and other objects, features, and advantages of the invention are accomplished by a method for selectively blocking angled ion implants on a semiconductor substrate. The method includes providing a semiconductor substrate having a surface. A first structure and a second structure are formed on the surface of the substrate. A first barrier is selectively formed adjacent a first side of the first structure. A dopant is implanted at an angle, however the barrier shadows the dopant from a portion of the first structure and no barrier shadows dopant from a corresponding portion of the second structure.
The present invention also includes symmetrical and asymmetrical semiconductor devices on the same wafer. Most typically, this will include a field effect transistor, having an LDD on the drain side of the gate, but not on the source side of the gate, or having a halo on the source side of the gate, but not on the drain side of the gate, or both; or a second set of devices having no halo implant in the source/drain, or a set of devices having no LDD implant in the source/drain.
Although the present invention may find application in various types of ion implanted semiconductor devices, the invention will be described here in connection with its application in MOSFET technology in which the structures on the semiconductor surface are the gates of MOSFETs.